| 摘要 |
<p>A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the memory elements; (60) performing a capture operation, (68) including configuring in capture mode throughout the capture operation, (64) non-source elements and multi-cycle path source elements which have a predetermined maximum capture clock rate which is the same as or higher than the capture clock rate (74); and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source elements which have a predetermined maximum capture clock rate which is lower than the capture clock rate; applying at least two clock cycles of the capture clock; and unloading test response data captured by the memory elements.</p> |
