发明名称 |
Integrated circuit with multi-voltage input/output (I/O) cells |
摘要 |
An integrated circuit (IC) includes a first I/O cell, a logic cell, a trigger signal generation circuit, and a second I/O cell having a voltage selection pin. I/O interfaces of the first I/O cell receive first and second supply voltages, respectively, and I/O interfaces of the second I/O cell receive third and fourth supply voltages, respectively. The first I/O cell generates a first trigger signal when the first supply voltage reaches a first predetermined voltage. The logic cell receives the first trigger signal and generates a safe-state signal. The trigger signal generation circuit generates a second trigger signal when the third supply voltage reaches a second predetermined voltage. The voltage selection pin receives the safe-state signal and the second trigger signal and sets the second I/O cell in a safe-state mode, which protects the second I/O cell from over voltage damage. |
申请公布号 |
US9383794(B2) |
申请公布日期 |
2016.07.05 |
申请号 |
US201414568074 |
申请日期 |
2014.12.11 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
Aggarwal Amit;Gupta Rohit;Malhotra Ashish;Malkov Andrey;Shevchenko Evgeny A. |
分类号 |
G06F1/26;G06F1/28 |
主分类号 |
G06F1/26 |
代理机构 |
|
代理人 |
Bergere Charles E. |
主权项 |
1. An integrated circuit (IC), comprising:
a first input/output (I/O) cell that has an input interface for receiving a first supply voltage, an output interface for receiving a second supply voltage, and means for generating a first trigger signal when the first supply voltage reaches a first predetermined voltage; a logic cell connected to the first I/O cell for receiving the first trigger signal, and outputting a safe-state signal; a trigger signal generation circuit for receiving a third supply voltage and outputting a second trigger signal when the third supply voltage reaches a second predetermined voltage; and a second I/O cell, connected to the trigger signal generation circuit, that has an input interface for receiving the third supply voltage, an output interface for receiving a fourth supply voltage, a logic gate that receives the safe-state signal and the second trigger signal, and a voltage selection pin connected to an output of the logic gate for setting the second I/O cell in a safe-state mode. |
地址 |
Austin TX US |