Transition between states in a processor

摘要

In one implementation, a processor is provided that includes logic to enable a transition from a zeroize state to a clear state. In another implementation, a processor is provided that includes logic to enable a testing secure state, the testing state to enable a testing function; logic to enable a clear state, the clear state to enable a non-secure processing function and to disable a security function; logic to enable a transition from a testing secure state to a clear state; and logic to enable a full secure state, the full secure state to enable the processing function. In another implementation, a processor is provided that includes logic to disable a transition from a clear state to a secure state.

主权项

1. An apparatus, comprising:
a processor that
enables a clear state, the clear state to enable a non-secure processing function and to disable a security function;enables a secure state that comprises a temporary secure state and a non-volatile secure state, the secure state to enable a secure processing function;enables a transition from the temporary secure state to the clear state, wherein the transition to the clear state from the temporary secure state is enabled based on a reset pulse; andenables a transition from the non-volatile secure state to the clear state, wherein the transition to the clear state from the non-volatile secure state is enabled based on a power loss.