| 摘要 |
PURPOSE:To obtain the discriminating signal being free from a discrimination error by executing the control so that phases of a synchronizing signal (discrimination clock signal) and a serial logical signal (input data signal) have a margin before an FF circuit latches erroneous data. CONSTITUTION:A serial logical signal (input data signal) (a) and a synchronizing signal (discrimination clock signal) (b) inputted to a phase detecting circuit 12 are converted to signals (c), (d) and (e) by delaying circuits 5 - 7, and inputted to F/F circuits 9, 10 and 8. The circuits 8 - 10 output latch signals (h), (g) and (f) of the signals (a), (c) and (d) by synchronizing with the discrimination clock signal (e). When a phase margin of the signals (c), (e) or the signals (d), (e) becomes below t0 time, the circuit 8 or 10 latches data being different from the circuit 9. The latch signal (g) of the signal (c) is a discriminating signal. The signals (f), (g) and (h) are inputted to a comparing circuit 11, and the circuit 11 outputs a signal (j) of H for showing a fact that a phase margin of the signal (c) does not exist from a terminal 3 to the signal (e) being an output of the circuit 7, and when a phase margin of the signal (d) does not exist with respect to the signal (e), a signal (k) of H is outputted to a terminal 4. |
