Multiple output offset comparator

摘要

A multiple output comparator compares a first input signal and a second input signal. An output mirror circuit receives the comparison and sets an output signal at a first output terminal of the multiple output comparator to a digital state indicating that the magnitude of the is greater than or lesser than the second signal. An offset generator creates an offset signal for adjusting a threshold signal level at the output mirror circuit such that the difference of the and the second signal is combined with the offset signal. The output mirror circuit transfers provides a digital state to another output terminal indicating that the is greater than or lesser than the second signal as adjusted by the adjustment signal.

主权项

1. A multiple output comparator configured to compare a first input signal with a second input signal and at least one threshold offset voltage level, comprising:
a difference circuit configured to receive a first input signal and a second input signal to determine when a magnitude of the first input signal is greater than or lesser than the second input signal and configured to provide a true output signal and a complement output signal that are indicative that magnitude of the first input signal is greater than or lesser than the second input signal; an output mirror driver circuit in communication with the difference circuit for receiving the true output signal and the complement output signal comprising:
a first mirror circuit configured for receiving the true output signal from the difference circuit and configured for generating at least one mirrored true output signal indicating that the first input signal is greater than or lesser than the second input signal;a second mirror circuit configured for receiving the complement output signal from the difference circuit and configured for generating at least one mirrored complement output signal indicating that the first input signal is greater than or lesser than the second input signal as offset by the at least one threshold offset voltage level wherein the at least one mirrored complement output signal is combined with an associated at least one mirrored in-phase reference signal to form a plurality of digital output signals; andat least one offset generator in communication with the second mirror circuit and configured for accurately generating the at least one threshold offset voltage level to ensure that the first input signal is greater than or lesser than the second input signal as offset by the at least one threshold offset voltage level.