发明名称 METHOD FOR FORMING DUAL DAMASCENE PATTERN TO PREVENT VIA FACETING PHENOMENON AND VIA BOWING PHENOMENON CAUSED BY DIFFERENCE OF VIA HOLE DENSITY AND AVOID INCREASE OF DIELECTRIC CONSTANT OF LOW-K INTERLAYER DIELECTRIC
摘要 PURPOSE: A method for forming a dual damascene pattern is provided to prevent a via faceting phenomenon and a via bowing phenomenon caused by a difference of a via hole density and avoid an increase of the dielectric constant of a low-k interlayer dielectric by preventing the low-k interlayer dielectric and a lower interconnection from being exposed to oxygen plasma used for removing an organic bottom ARC(anti-reflective coating). CONSTITUTION: A diffusion barrier layer(12), an interlayer dielectric(13) and a capping layer(14) are formed on a substrate(10) having an interconnection. The exposed portions of the capping layer and the interlayer dielectric are etched to form a via hole(16) by a via hole etch process. A nitride spacer is formed on the sidewall of the via hole. An organic bottom ARC is formed on the resultant structure. The exposed portions of the organic bottom ARC, the capping layer and the interlayer dielectric are etched by a predetermined depth to form a trench(19) by a trench etch process. The nitride spacer is removed. The diffusion barrier layer exposed to the bottom of the via hole is eliminated.
申请公布号 KR20050017844(A) 申请公布日期 2005.02.23
申请号 KR20030055297 申请日期 2003.08.11
申请人 MAGNACHIP SEMICONDUCTOR, LTD. 发明人 YOON, JUN HO
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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