| 摘要 |
An analog-to-digital conversion method is provided to improve sampling accuracy by completely separating an input signal from a background noise by using an operational amplifier with a large CMRR(Common Mode Rejection Ratio). An input signal(204) is inputted to plural ADC(Analog Digital Converter) cells(202a-202n) on a chip(201). A sampling clock is one twenties to one tenth the frequency of a desired sampling ratio. Time distributors(206a-206n) provide sequential time periods. An ADC(202) samples the input signal at a slightly delayed point. Tap line connections(207a-207n) are formed between respective distribution stations and corresponding ADCs. A timing signal, which is provided by the sampling clock, passes through the time distributors, and a series of taps or prompts are transmitted to the respective ADCs through the tap line connections.
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