发明名称 Biasing and sizing of the MOS transistor in weak inversion for low voltage applications
摘要 Methods and circuits are disclosed for low voltage (1.5 Volt and below) CMOS circuits, offering good transconductance and current driving capabilities. These goals are achieved by biasing CMOS transistors in the weak inversion region, by utilizing multiple unit-sized transistors with a fixed gate width to gate length ratio, and by maintaining a uniform threshold voltage of each unit-sized transistor. The required transistor size is obtained by parallel connection of several unit-sized transistors, such that 'n' unit sized transistors carry the required current of 'n' units. The methods and circuits disclosed eliminate deviation of the output current of current mirrors caused by threshold voltage mismatch. Disclosed are a current mirror and two typical amplifiers as examples of weak inversion design.
申请公布号 US6157259(A) 申请公布日期 2000.12.05
申请号 US19990292359 申请日期 1999.04.15
申请人 TRITECH MICROELECTRONICS, LTD. 发明人 DASGUPTA, UDAY
分类号 H03F3/345;H03F3/45;(IPC1-7):H03F3/04 主分类号 H03F3/345
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