| 摘要 |
<p>PURPOSE: To reduce power consumption by receiving data of a register corresponding to count of a counter counting number of 1st clock signals. CONSTITUTION: A flip-flop 51 gives data received at an input terminal 28 to registers 31-34 with a delayed timing by one clock based on a 1st clock WCL. On the other hand, four outputs of a decoder 23 and the clock WCL are given to gates 52-54 and their outputs are used to receive data for the registers 31-34. The output of count 0 among outputs of the decoder 23 is given to the register 34 vi a gate 55 and outputs of counts 1, 2, 3 are fed to the registers 31-34 via gates 52-54. Thus, input data are received only one of the registers 31-34 corresponding to the count of the counter 15 in this way and the data are not received by the other registers. Thus, power consumption is reduced.</p> |
