| 摘要 |
PURPOSE: An instruction decoder is provided to reduce a instruction decoding path by remove a critical path for decoding the instruction in microprocessor operating at high speed. CONSTITUTION: The instruction decoder comprises a prefetch unit(210); an instruction que unit(220) and a decoding unit(230). In the instruction decoder, in response to cache hit signal or cache miss signal output from a cache unit(200), on cache hit, the prefetch unit receives a instruction line output from the cache unit, and on cache miss, the prefetch unit receives a instruction line which is accessed and input from external memory. From the received instruction lines, the prefetch checks whether the instruction to be executed in each pipeline can be executed in parallel or not, and predecodes the instruction. The instruction que unit stores the instruction which is output from the prefetch unit. The decoding unit finally decodes the instruction of each pipeline output from the instruction que unit, respectively. Thereby, it is possible to eliminate the critical decoding path so that it is can be executed a high speed operating stably.
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