发明名称 Method and apparatus for stacking core and uncore dies having landing slots
摘要 An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.
申请公布号 US9514093(B2) 申请公布日期 2016.12.06
申请号 US201414498353 申请日期 2014.09.26
申请人 Intel Corporation 发明人 Rusu Stefan
分类号 G06F15/76;H01L25/065 主分类号 G06F15/76
代理机构 Nicholson de Vos Webster & Elliot LLP 代理人 Nicholson de Vos Webster & Elliot LLP
主权项 1. An apparatus comprising: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die,power management logic to manage power usage by cores on the core die,a fully integrated voltage regulator (FIVR) to manage voltage levels on the core die and the uncore die, anda plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.
地址 Santa Clara CA US