发明名称 Dual processor retention module
摘要 A dual processor retention module for holding one or two edge connector processors. The dual processor retention module includes a first and second retention slot. Each retention slot includes a first and second horizontal bar, with each bar having a first end and a second end. Each retention slot also includes a first upright member connected to the first ends of the first and second horizontal bars, and a second upright member connected to the second ends of the first and second horizontal bars. The dual processor retention module has a first pair of connectors connecting the first upright members, and a second pair of connectors connecting the second upright members. The connectors are placed such that the horizontal bars for the first retention slot are parallel to the horizontal bars for the second retention slot.
申请公布号 US6155433(A) 申请公布日期 2000.12.05
申请号 US19970980847 申请日期 1997.12.01
申请人 INTEL CORPORATION 发明人 ANDERSON, PAUL H.;BENNETT, DOUGLAS G.;ROOT, WILLIAM E.
分类号 H01R12/18;H05K7/14;(IPC1-7):H01R13/62;A47F7/00 主分类号 H01R12/18
代理机构 代理人
主权项
地址