Method and Structure for III-V FinFET

摘要

A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the Ill-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.

主权项

1. An apparatus for a semiconductor device, comprising:
a substrate comprising a III-V compound semiconductor material; a plurality of fins formed in the III-V compound semiconductor material; a semiconductor extension on each of the fins, the semiconductor extensions each comprising a III-V compound semiconductor material that is different from a material forming the fins; a gate structure and a spacer across and perpendicular to the fins; a source/drain layer on a top surface of the substrate; and a planarization layer on a top surface of the source/drain layer; wherein the semiconductor extensions on each of the fins are etched from under the spacer to provide undercut regions beneath the spacer to expose a topmost surface of each fin to extend the gate/fin junction profile.