Slow to fast clock synchronization

摘要

A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.

主权项

1. An apparatus, comprising:
a first flip-flop circuit configured to sample data dependent upon a first clock signal to generate sampled data; a synchronizer circuit configured to generate a synchronized first clock signal dependent upon a second clock signal, wherein at least one transition of the synchronized first clock signal corresponds to a transition of the second clock signal, wherein a frequency of the first clock signal is lower than a frequency of the second clock signal; an edge detection circuit configured to:
detect an edge of the synchronized first clock signal; andassert an enable signal responsive to the detection of the edge of the synchronized first clock signal; and a second flip-flop circuit configured to capture, in response to the assertion of the enable signal, the sampled data dependent upon the second clock signal; wherein the synchronizer circuit comprises:
a third flip-flop circuit configured to sample the first clock dependent upon the second clock signal;a fourth flip-flop circuit configured to sample an output of the third flip-flop circuit dependent upon the second clock signal.