发明名称 CODE CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a code conversion circuit having a configuration for carrying out the code conversion of a signal of an NRZ code to a signal of another NRZ code, and capable of conducting code conversion processing at a working speed corresponding to a transmission rate or a working speed not higher than it. SOLUTION: The code conversion circuit comprises a demultiplexing portion 1 for separating a data signal of an NRZ code into a plurality of parallel data signals, a converting circuit 2 for inputting the plurality of separated parallel data signals, and a multiplexer 3 for multiplexing a plurality of parallel output data signals. The code conversion circuit has a configuration comprising a first exclusive-or circuit 12 for determining an exclusive OR of one data signal in the plurality of parallel data signals and a data signal obtained by delaying the other data signal by 1 bit by a delay circuit 11, a logical multiply circuit 13 for determining a logical product of an output signal of the first exclusive-or circuit 12 and a clock signal of a transmission rate of the parallel data signal, a T flip-flop 14 for inputting the output signal, and a second exclusive-or circuit 15 for determining an exclusive OR of a data signal of an NRZ code of the output signal and the other data signal. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006270735(A) 申请公布日期 2006.10.05
申请号 JP20050088223 申请日期 2005.03.25
申请人 FUJITSU LTD 发明人 KUWATA NAOKI
分类号 H04L25/49 主分类号 H04L25/49
代理机构 代理人
主权项
地址
您可能感兴趣的专利