MEMORY SYSTEM WITH MULTIPLE CHANNEL INTERFACES AND METHOD OF OPERATING SAME

摘要

A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

主权项

1. A memory system comprising:
a memory controller comprising a plurality of channel interfaces including a first channel interface and a second channel interface; a plurality of memories including a first memory group and a second memory group; a plurality of channels including a first channel connected to the first memory group and a second channel connected to the second memory group; and a plurality of channel interfaces disposed in the memory controller including a first channel interface and a second channel interface, wherein the first channel interface communicates first signals to the first memory group via the first channel synchronously with a first slave clock and the second channel interface communicates second signals to the second memory group via the second channel synchronously with a second slave clock having a different phase than the first slave clock, and the first slave clock is derived from a first input clock and the second slave clock is derived from a second input clock.