MULTI-RATE HIGH-SPEED BUS WITH STATISTICAL AGGREGATOR

摘要

A single high-speed bus accommodates both low-rate and high-rate bi-directional signal traffic by interleaving the traffic at the two rates sequentially so that all the data in the bus at any given time is either high-rate or low-rate. The interleaving is executed by a statistical aggregator according to a policy tailored to the traffic expected in the particular bus. The policy may be static and predetermined, or it may be dynamic and adaptive. Adaptive policies are continually updated with predictions of future traffic based on the statistics of past and/or present traffic. The technique may be implemented in both on-chip and system-level bus interfaces.

主权项

1. A device, comprising:
a traffic detector to determine if a high-speed packet is to be sent in a high speed transfer mode or if a low speed packet is to be sent in a low speed transfer mode; and a bus controller to be coupled to the traffic detector, the bus controller to implement a first communication protocol for a transmission of the high-speed packet that is to be sent in the high speed transfer mode and to implement a second communication protocol during a transmission of the low-speed packet that is to be sent in the low speed transfer mode.