PHASE DETECTION IN AN ANALOG CLOCK DATA RECOVERY CIRCUIT WITH DECISION FEEDBACK EQUALIZATION

摘要

An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

主权项

1. A circuit for phase detection, the circuit comprising:
a first summer circuit that subtracts odd-data feedback signals from a plurality of taps of a decision feedback equalizer from an analog data signal to obtain an odd-feedback partially-equalized data signal; a first sampling circuit that samples the odd-feedback partially-equalized data signal using a first quadrature clock signal to generate a first partial-equalization edge signal; a second sampling circuit that subtracts a feedback signal from a first tap of the decision feedback equalizer from the odd-feedback partially-equalized data signal to obtain an odd-feedback fully-equalized data signal and samples the odd-feedback fully-equalized data signal using the first quadrature clock signal to generate a first full-equalization edge signal; a second summer circuit that subtracts even-data feedback signals from the plurality of taps of the decision feedback equalizer from the analog data signal to obtain an even-feedback partially-equalized data signal; a third sampling circuit that samples the even-feedback partially-equalized data signal using a second quadrature clock signal to generate a second partial-equalization edge signal; a fourth sampling circuit that subtracts the feedback signal from the first tap of the decision feedback equalizer from the even-feedback partially-equalized data signal to obtain an even-feedback fully-equalized data signal and samples the even-feedback fully-equalized data signal using the second quadrature clock signal to generate a second full-equalization edge signal; and a fifth sampling circuit that subtracts the feedback signal from the first tap of the decision feedback equalizer from the odd-feedback partially-equalized data signal to obtain the odd-feedback fully-equalized data signal and samples the odd-feedback fully-equalized data signal using a third quadrature clock signal to generate an even data signal.