| 摘要 |
PURPOSE:To attain a reading even when the same address is changed for a short time by detecting the transition of an address and resetting a preamplifier activating signal generating circuit and a resetting signal generating circuit while a first fine single pulse is generated. CONSTITUTION:When an address Ai is transited and the output ATD of an address transition detecting circuit 100 goes to a high level, a column decoder activating signal, the inverse of ATD' goes to a low level and bit line pair data are transferred through a selecting column decoder to an I/O line pair. Thereafter, when a signal ATD goes to a low level, a signal ATDD goes to a high level, further, a preamplifying activating signal PAE' goes to the high level and a resetting signal CDC goes to the high level by the delaying from the signal PAE'. When the same address is changed within a short time again, the output ATD goes to the high level again and a preamplifying activating signal generating circuit 200b and a resetting signal generating circuit 200c are reset. Thereafter, the low level of the signal ATD is detected, and thus, reading can be executed normally.
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