发明名称 DATA ACCESS CONTROL METHOD BY TAMPER-RESISTANT MICROPROCESSOR AND CACHE MEMORY MOUNT PROCESSOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a data access control method by a tamper-resistant microprocessor and a cache memory mount processor without the need for a complicated hardware function wherein contents of a cache memory can be read from other programs with a secure method when a plurality of programs share one encryption key without the access limit of the cache memory and without the need for scanning all areas of the cache memory. <P>SOLUTION: The tamper-resistant microprocessor 100 is provided with: a processor core 10; a cache memory control section 20; a code data encryption decryption processing section 30; and a key value register 40 or the like. The key value register 40 stores the encryption key. The encryption key is also stored in privacy protection attribute storage sections 25a to 25d on a cache line for storing execution codes and data. The cache memory control section 20 compares contents of the key value register 40 with contents of the privacy protection attribute storage sections 25a to 25d to perform identity discrimination processing of the execution codes and the data. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p>
申请公布号 JP2004228786(A) 申请公布日期 2004.08.12
申请号 JP20030012558 申请日期 2003.01.21
申请人 TOSHIBA CORP 发明人 YAMAGUCHI KENSAKU;HASHIMOTO MIKIO
分类号 G06F12/08;G06F12/14;G06F21/00;G06F21/22;H04L9/10;(IPC1-7):H04L9/10;G06F1/00 主分类号 G06F12/08
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