发明名称 INCREMENTAL LOGIC GENERATION METHOD
摘要 PROBLEM TO BE SOLVED: To enable an FF precisely correspond to port, to make the circuit structure of an old logical circuit where ports are split preservable and to make a design change of a circuit structure which does not change its function reflectable in an updated circuit. SOLUTION: An incremental logic generation method has a step for making Flip Flop(FF) correspond to port which inputs an old logical circuit and a new logical circuit from an old logical circuit file 105 and a new logical circuit file 106, inputs correspondence exclusion signal name information from an external information file 108 and makes FF/port correspond to each other, a recognition step for a logic equivalence pair which inputs logic equivalence attribute information from an external information file 109 and recognizes the logic equivalence pair of the old logical circuit and the new logical circuit, a logic merge step which inputs updated circuit element information from an external information file 110 and merges the old logical circuit and the new logical circuit, and a logic optimization step which inputs a restriction from an external information file 111, performs logic optimization of a logical circuit merged at the logic merge step and outputs the updated logical circuit.
申请公布号 JP2000003382(A) 申请公布日期 2000.01.07
申请号 JP19980179704 申请日期 1998.06.11
申请人 HITACHI LTD 发明人 SAKAKI HIROMOTO;HAYASHI NOBUYUKI;TANDAI MIYAKO;ISHIDA TOMOKO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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