| 摘要 |
PROBLEM TO BE SOLVED: To obtain a direct memory access controller that sequentially transfers two-dimensionally arrayed data, in response to one direct memory access transfer request. SOLUTION: This direct memory access controller is provided with an offset address generation circuit 54, for generating an offset value of a current address based on the number of columns set in the number of block columns register 21, the number of rows set in the number of block rows register 24 and the number of blocks set in the number of blocks register 27, according to the direction to be rotated which is set in a rotation mode register 51, when data transfer for one row of one block is finished, and when data transfer for one block is finished or when block transfer for one line is finished.
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