| 摘要 |
PURPOSE:To eliminate the need for an attached circuit, to increase an operation speed, and to reduce a circuit pattern area and the cost by reducing kinds of input signals to a logical setting circuit which is the constitution of the titled device. CONSTITUTION:The logical setting circuit 21 wherein plural logical arithmetic input signals are led to an enhancement N type MOSFET and a depletion P type MOSFET is provided. Further, the 2nd logical setting circuit 22 which includes an enhancement N type MOSFETM1 applied with a synchronizing signal at its gate and an enhancement P type MOSFET and a depletion N type MOSFET supplied with the same input signals with the 1st logical setting circuit and have different logical setting condition is provided. Then, a CMOS logical circuit is composed of an enhancement P type MOSFETM6 applied with an inverted synchronizing signal at its gate; kinds of input signals are reduced, the need for an added circuit is eliminated, and the operation speed is increased. |
