| 摘要 |
To provide a received data recovering device that can follow a rapid change in phase of data in data communication, thereby to prevent lowering of the data transmission efficiency. A receiving device 10 samples a baseband signal 14a in a shift register group 16a of a clock phase detecting circuit 16 using an N-times (N is an integer equal to or greater than 2) frequency relative to the baseband signal 14a, and outputs to a field phase detecting circuit 16A the number of bits required by each of fields per N. In the field phase detecting circuit 16A, not only hitherto detection of a synchronization word is implemented, but also detection of error data with respect to fields of a packet header and an FEC (Forward Error Correction) code is implemented depending on existence of data. While confirming that correct reception is implemented per field, by performing the foregoing detection, the optimum clock phase is determined and corresponding clock phase information 16h is outputted to a FIFO 18, thereby to more stabilize a received symbol 18a read out from the FIFO 18.
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