Motor drive control device and operation method thereof

摘要

When a motor drive control device is integrated in a semiconductor integrated circuit having a small chip area, calibration for improving the accuracy of detection of a counter electromotive voltage, which is for detecting the speed of a motor, is enabled. A first multiplier performs multiplication between a drive current detection signal and first gain information in a first register. A subtractor performs subtraction between a drive voltage command signal and a first multiplication result in the first multiplier. A second multiplier performs multiplication between a subtraction result in the subtractor and second gain information in a second register to generate counter electromotive voltage information as information on a second multiplication result. The drive voltage command signal in a control unit is set to a predetermined value to generate a condition which maintains the speed of the motor and a counter electromotive voltage at substantially zero.

主权项

1. A semiconductor device including a motor drive control device, the motor drive control device comprising:
a digital control unit configured to generate a digital drive voltage command signal; a digital-to-analog converter configured to respond to the digital drive voltage command signal to generate an analog drive voltage command signal; a driver output unit configured to couple with a motor and a detection resistor in series, which is configured to respond to the analog drive voltage command signal to generate a drive output signal for driving the motor; a drive current detection amplifier configured to respond to a drive current flowing in the detection resistor to generate a drive current analog amplified signal; an analog-to-digital converter configured to respond to the drive current analog amplified signal to generate a digital drive current detection signal; a counter electromotive voltage detection unit including a first digital multiplier, a digital subtractor, a second digital multiplier, a first register, and a second register,
the first digital multiplier performing multiplication between the digital drive current detection signal and first gain information stored in the first register to generate a first multiplication result,the digital subtractor performing subtraction between the digital drive voltage command signal and the first multiplication result to generate a subtraction result N;the second digital multiplier performing multiplication between the subtraction result and second gain information stored in the second register to generate digital counter electromotive voltage information as information on a second multiplication result, wherein the digital drive voltage command signal is set to a predetermined value to allow a condition which maintains a speed of the motor and a counter electromotive voltage at substantially zero to be generated, wherein, under the condition, the first gain information which sets a value of the digital counter electromotive voltage information to substantially zero is allowed to be stored in the first register.