| 摘要 |
PURPOSE:To prevent mixing of preceding data and next data by transferring next data after a data reception completion signal from the slave side is received with respect to data transfer from a master microprocessor to a slave microprocessor. CONSTITUTION:A master microprocessor MPU1 transfers data to a buffer memory 3' in the direct memory access DMA mode, and a data read request signal 3 is transmitted from the buffer memory 3' to a slave MPU4' when the last data is transferred completely. Simultaneously, a data transfer completion report signal 2 is transmitted from a DMA control part DMAC2' to the buffer memory 3'. The slave MPU4' reads data stored in the buffer memory 3' by the data read request signal 3. The buffer memory 3' transmits a last data read completion report signal 4 to the master MPU1 by the start of read of the last data due to the slave MPU4'. The master MPU1 starts the next data transfer operation after receiving the last data read completion report signal 4. Thus, mixing of preceding data and next data is prevented. |
