| 摘要 |
PROBLEM TO BE SOLVED: To provide a duty correction voltage generating circuit capable of speedily normalizing a duty correction voltage used to decrease the duty error of a clock in the initial status of a delay locked loop. SOLUTION: The duty correction voltage generating circuit which corrects the duty of a clock used for the delayed locked loop comprises: a control signal generating means (510) which generates and outputs a control signal (chg-s) for maintaining a first logical level for a predetermined time in response to a reset signal (rst) for resetting an inputted delay locked loop; and a power supply voltage supplying means (520) which supplies a power supply voltage (Vdd) for a predetermined time to an output line of duty correction voltages (Vdcc, Vdcb) used to correct the duty of the clock in response to the inputted control signal (chg-s). COPYRIGHT: (C)2005,JPO&NCIPI
|
