| 摘要 |
An input network phase shifts received signals by substantially 180 DEG and also attenuates received signals as a function of the frequency. A summing circuit receives the phase shifted signal as well as the unaltered received signal, to develop signals as a function of the instantaneous difference in amplitude between them. The summing circuit includes a constant current sink connecting it to ground and a constant voltage device connecting the low potential side of the summing circuit to the low potential side of the unaltered received signals as a reference. In its preferred embodiment the frequency change detector is capable of detecting such frequency changes within one cycle of the received signals for frequencies ranging from dc to the multi-MHz range.
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