| 摘要 |
PURPOSE:To reduce considerably the chip area of a highly integrated IC having a dielectric strength of 12V and 16V by operating the inside of the IC with a normal low voltage and operating an input/output part with a power source voltage common to an external circuit. CONSTITUTION:When the potential difference between a high power voltage input terminal VDD and a low power terminal VSS exceeds VTP+VTN (VTP and VTN are threshold voltges of a P-MOS and an N-MOS), a current starts flowing through a resistance 4, an MOS5, an MOS6, and a resistance 7. When this potential difference is increased furthermore, the current is flowed to even an MOS3. Therefore, the source potential of the MOS5 is limited, and this potential difference is saturated. Since this limited potential difference is the sum of diode characteristics VfP and NfN of MOSs 3 and 5, a C-MOS is operated surely if a voltage (VfP+VfN) between terminals VDD1 and VSS'11 is applied. Consequently, it is sufficient if the C-MOS having a low dielectric strength is used in an internal logic circuit, and the chip area is reduced. |
