| 摘要 |
An apparatus has a processing pipeline 4 supporting first and second processing modes with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44 Fig. 1) is accessible in both processing modes. When the second processing mode is selected, control circuitry triggers a subset of the entries of the storage structure to be placed in a power saving state. The first processing mode may have greater maximum throughput of instructions than the second processing mode. On switching from first to second processing mode, control circuitry may disable further allocation of information to the subset of entries, and prevent the pipeline accessing information in the subset. The control circuitry may place a subset of entries in the power saving state in response to an indication that the pipeline no longer requires the subset. The pipeline may support out-of-order execution in both first and second processing modes, and the storage structure may comprise a reorder buffer to store information for tracking completion of instruction-execution. |
