发明名称 STABLE PROBING-RESILIENT PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT
摘要 Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
申请公布号 US2017111180(A1) 申请公布日期 2017.04.20
申请号 US201615335158 申请日期 2016.10.26
申请人 Intel Corporation 发明人 Mathew Sanu K.;Satpathy Sudhir K.
分类号 H04L9/32;H03K19/177 主分类号 H04L9/32
代理机构 代理人
主权项 1. A physically unclonable function (PUF) circuit comprising: a bit node and a bit bar node; a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node; a first pre-charge transistor coupled between the bit node and a power supply rail; a second pre-charge transistor coupled between the bit bar node and the power supply rail, the first and second pre-charge transistors to receive a clock signal via respective first and second clock paths; a first delay chain disposed on the first clock path; a second delay chain disposed on the second clock path; and control circuitry to: pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; andwrite a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value to provide a differential delay in the first and second clock paths.
地址 Santa Clara CA US