发明名称 Cache partitioning in a multicore processor
摘要 Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.
申请公布号 US9612961(B2) 申请公布日期 2017.04.04
申请号 US201314363792 申请日期 2013.08.29
申请人 EMPIRE TECHNOLOGY DEVELOPMENT LLC 发明人 Solihin Yan
分类号 G06F12/08;G06F12/0842;G06F1/32;G06F12/0875;G06F12/126;G06F15/173;G06F9/50 主分类号 G06F12/08
代理机构 Ren-Sheng International 代理人 Ren-Sheng International
主权项 1. A method to update a cache in a multi-core processor, the method comprising: receiving a notification of a cache miss associated with a process or a thread running on a single core of the multi-core processor, the single core including: a first cache partition from which the single core can read data and to which the single core can store data from a first data source, anda second cache partition from which the single core can read data and to which the single core can store data from a second data source; determining that an address associated with the cache miss corresponds to the first data source; and storing data associated with the cache miss in the first cache partition, wherein storing data associated with the cache miss in the first cache partition comprises comparing a current size of the first cache partition with a target size of the first cache partition, and, in response to the current size of the first cache partition being less than the target size, increasing the current size of the first cache partition by evicting data associated with the second cache partition.
地址 Wilmington DE US