| 主权项 |
1. A computer system comprising:
one or more computer processors; one or more non-transitory computer readable storage media; program instructions stored on at least one of the one or more non-transitory computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
program instructions to instruct a mail handler to manage a source queue for incoming messages from one or more agents, the source queue having a first count of slots and being associated with a source read pointer and a source write pointer, wherein a first logical unit of the mail handler is instructed to manage the source write pointer and a second logical unit of the mail handler is instructed to manage the source read pointer;program instructions to instruct the mail handler to manage a destination queue for outgoing messages to at least one computer processor, the destination queue having a second count of slots and being associated with a destination read pointer and a destination write pointer, wherein the second logical unit is instructed to manage the destination write pointer and the at least one computer processor is instructed to advance the destination read pointer in response to reading at least one message from the destination queue;program instructions to instruct the first logical unit to read a first queue port register value from a queue port register, wherein:
a queue port register value equal to either zero or negative one indicates a count equal to one; anda queue port register value of less than negative one indicates a count equal to an absolute value of the queue port register value;program instructions to instruct the first logical unit to determine that the mail handler is to transfer a first set of one or more messages from the source queue to the destination queue based, at least in part, on the first queue port register value, wherein the first queue port register value is greater than zero, and in response, instruct the first logical unit to:
advance the source write pointer by a count of slots that is equal to the first queue port register value; andset a value of a first register of the mail handler to the first queue port register value plus an initial value of the first register, wherein the initial value of the first register is a value of the first register prior to reading the first queue port register value, and the value of the first register indicates a count of pending messages to transfer from the source queue to the destination queue before reserving slots in the destination queue;program instructions to instruct the second logical unit to determine that the mail handler is to transfer the first set of one or more messages from the source queue to the destination queue based, at least in part, on the value of the first register, wherein the value of the first register is greater than zero, and in response, instruct the second logical unit to:
lock the first logical unit;transfer one or more messages from the source queue to the destination queue based, at least in part, on the value of the first register, wherein a count of the one or more messages transferred from the source queue to the destination queue is less than or equal to a count of messages in the first set of one or more messages;advance each of the source read pointer and the destination write pointer by an amount equal to the count of the one or more messages transferred from the source queue to the destination queue;set the value of the first register to the value of the first register minus the count of the one or more messages transferred from the source queue to the destination queue; andunlock the first logical unit;program instructions to instruct the first logical unit to read a second queue port register value from the queue port register;program instructions to instruct the first logical unit to determine that the mail handler is to transfer a second set of one or more messages from the source queue to the destination queue based, at least in part, on the second queue port register value, wherein the second queue port register value is greater than zero, and in response, instruct the first logical unit to:
advance the source write pointer by an amount equal to the second queue port register value; anddetermine that a value of a second register of the mail handler is not equal to zero, wherein (i) the value of the second register indicates a count of slots in the destination queue to reserve, and (ii) the value of the second register is based, at least in part, on a request of the at least one processor, and in response, instruct the first logical unit to:
set a value of a third register to the second queue port register value plus a previous value of the third register, wherein the previous value of the third register is a value of the third register prior to reading the second queue port register value, and the value of the third register indicates a count of messages to transfer from the source queue to the destination queue after reserving a count of slots in the destination queue; andprogram instructions to instruct the second logical unit to determine that the mail handler is to reserve one or more slots in the destination queue based, at least in part, on the value of the second register, and in response, instruct the second logical unit to:
lock the first logical unit;reserve the one or more of slots in the destination queue by advancing the destination write pointer by an amount equal to a count of the one or more slots;provide at least one memory address to the at least one processor, wherein the at least one memory address enables the at least one processor to identify the one or more slots;set the value of the second register to the value of the second register minus a count of the one or more slots reserved in the destination queue;set the value of the first register to the value of the third register;set the value of the third register to zero; andunlock the first logical unit. |
