High-speed low-power LDPC decoder design

摘要

Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.

主权项

1. A system for decoding an LDPC encoded codeword, comprising:
variable nodes, the variable nodes correspond to columns of a parity check matrix of the LDPC encoded codeword, and are divided into a plurality of groups; check nodes, the check nodes correspond to rows of the parity check matrix of the LDPC encoded codeword; a variable node updater configured to update a selected group of the variable nodes from the plurality of groups of the variable nodes, the variable node updater generates input values from the selected group of the variable nodes to correlated check nodes thereof, and decoded values from the selected group of the variable nodes; a check node updater configured to update the check nodes using a min-sum update, the check nodes receive corresponding input values from correlated variable nodes, a portion of the corresponding input values of the selected group of the variable nodes is saved for use in a future min-sum update as saved input values; and a codeword updater configured to calculate codewords in accordance with the decoded values, and output a decoded codeword when the codewords are error free.