Packaging solutions for devices and systems comprising lateral GaN power transistors

摘要

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

主权项

1. A semiconductor device structure comprising an assembly of:
a lateral Gallium Nitride power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers; the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the GaN die being sandwiched between the first and second leadframe layers; the first leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die; the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material; the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the first leadframe layer by low inductance interconnections; and a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the source, drain and gate of the lateral GaN transistor.