发明名称 |
Three-dimensional semiconductor memory device |
摘要 |
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures. |
申请公布号 |
US9559111(B2) |
申请公布日期 |
2017.01.31 |
申请号 |
US201514790969 |
申请日期 |
2015.07.02 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Yoo Dongchul;Nam Phil Ouk;Yang Junkyu;Lee Woong;Lee Woosung;Kim JinGyun;Eom Daehong |
分类号 |
H01L29/792;H01L27/115;H01L29/423 |
主分类号 |
H01L29/792 |
代理机构 |
Lee & Morse, P.C. |
代理人 |
Lee & Morse, P.C. |
主权项 |
1. A three-dimensional (3D) semiconductor memory device, comprising:
a lower structure including a lower gate pattern and a lower semiconductor pattern penetrating the lower gate pattern, the lower semiconductor pattern being connected to a substrate; and an upper structure including upper gate patterns stacked on the lower structure, an upper semiconductor pattern penetrating the upper gate patterns, and a vertical insulator between the upper semiconductor pattern and the upper gate patterns, the upper semiconductor pattern being connected to the lower semiconductor pattern, wherein the lower semiconductor pattern has a rounded sidewall adjacent to the lower gate pattern, and wherein the lower semiconductor pattern includes an epitaxial pattern. |
地址 |
Suwon-Si, Gyeonggi-Do KR |