EDGELESS LARGE AREA ASIC

摘要

A three dimensional integrated edgeless pixel detector apparatus can be implemented, which includes a multi-tiered three-dimensional detector having one sensor layer, and two ASIC layers comprising an analog tier and a digital tier configured for x-ray photon time of arrival measurement and Imaging. In a preferred embodiment, a hit processor can be implemented in association with a priority encoder and a configuration register and output serializer with mode selection.

主权项

1. A three-dimensional integrated edgeless pixel detector apparatus, comprising:
a large area multi-tier three-dimensional detector having a sensor layer; and at least two ASIC layers comprising at least one analog tier and at least one digital tier configured for radiation spectroscopy or imaging with zero suppressed or full frame readout.