发明名称 Ohmic contact to semiconductor
摘要 A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.
申请公布号 US9543400(B2) 申请公布日期 2017.01.10
申请号 US201514973563 申请日期 2015.12.17
申请人 Sensor Electronics Technology, Inc. 发明人 Gaska Remigijus;Shur Michael;Yang Jinwei;Dobrinsky Alexander;Shatalov Maxim S.
分类号 H01L31/072;H01L29/45;H01L29/66;H01L29/778;H01L21/285;H01L29/40;H01L33/00;H01L29/15;H01L29/20;H01L29/205;H01L33/14;H01L29/737;H01L33/06;H01L33/32;H01L29/201;H01L33/40 主分类号 H01L31/072
代理机构 LaBatt, LLC 代理人 LaBatt, LLC
主权项 1. A device heterostructure comprising: a semiconductor layer; a protruded region located directly on a first region of a surface of the semiconductor layer; and an ohmic contact located on a set of contact regions of the surface of the semiconductor layer distinct from the first region of the surface of the semiconductor layer, wherein the ohmic contact is formed without etching the semiconductor layer, and wherein the forming includes: forming a set of highly conductive semiconducting layers on the set of contact regions, wherein the forming the set of highly conductive semiconducting layers includes grading a molar fraction of at least one element of a material forming the set of highly conductive semiconducting layers with respect to a distance from the set of contact regions; andforming an ohmic metal on the set of highly conductive semiconducting layers after formation of the protruded region, wherein the forming the ohmic contact is performed at a processing temperature lower than a temperature range within which a quality of a material forming any one of the set of semiconductor layers in the device heterostructure is damaged.
地址 Columbia SC US