MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF

摘要

The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52′) with ion doping process, and the oxide conductor layer (52′) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

主权项

1. A manufacture method of a dual gate oxide semiconductor TFT substrate, comprising steps of:
step 1, providing a substrate, and deposing a first metal layer on the substrate, and implementing pattern process to the first metal layer with a first photo process to form a bottom gate; step 2, deposing a bottom gate isolation layer on the bottom gate and the substrate; step 3, deposing a color resist layer on the bottom gate isolation layer, and sequentially implementing pattern processes to the color resist layer with second, third and fourth photo processes to form red/green/blue color resist layers; then, deposing a flat layer on the red/green/blue color resist layers, and implementing pattern process to the flat layer with a fifth photo process to form flat layers respectively covering the red/green/blue color resist layers; step 4, deposing an oxide semiconductor layer on the bottom gate isolation layer and the flat layers, and coating a photoresist layer on the oxide semiconductor layer, and employing a halftone mask to implement a sixth photo process: first, implementing exposure, development to the photoresist layer to obtain a first photoresist layer and a second photoresist layer respectively positioned above the bottom gate and the flat layers and covering the oxide semiconductor layer; a thickness of two side areas of the first photoresist layer and a thickness of the second photoresist layer are smaller than a thickness of a middle area of the first photoresist layer; employing the first photoresist layer and the second photoresist layer to implement etching the oxide semiconductor layer for patterning the oxide semiconductor layer to respectively obtain a first oxide semiconductor layer and a second oxide semiconductor layer on the bottom gate and the flat layers; step 5, first, removing the two side areas of the first photoresist layer and the second photoresist layer; employing the remaining middle area of the first photoresist layer as being a mask layer to implement ion doping to the two side areas of the first oxide semiconductor layer and the second oxide semiconductor layer, to transform the two side areas of the first oxide semiconductor layer to be a conductor, and to transform the second oxide semiconductor layer to be an oxide conductor layer; then, removing the remaining middle area of the first photoresist layer; step 6, deposing a top gate isolation layer on the first oxide semiconductor layer, the oxide conductor layer and the bottom gate isolation layer, and implementing pattern process to the top gate isolation layer with a seventh photo process, to respectively form first via holes above the two side areas of the first oxide semiconductor layer and a second via hole above the oxide conductor layer; step 7, deposing second, third metal layers on the top gate isolation layer, and implementing pattern process to the second, third metal layers with an eighth photo process, to respectively obtain a top gate above the first oxide semiconductor layer and a source and a drain at two sides of the top gate; the source and the drain respectively contact with the two side areas of the first oxide semiconductor layer through the first via holes, and the source contacts with the oxide conductor layer through the second via hole; step 8, deposing a passivation layer on the top gate, the source, the drain and the top gate isolation layer; implementing pattern process to the passivation layer and the top gate isolation layer at the same time with a ninth photo process to obtain a third via above the oxide conductor layer to expose a portion of the oxide conductor layer; the bottom gate, the first oxide semiconductor layer, the source, the drain and the top gate construct a dual gate TFT; the oxide conductor layer constructs a pixel electrode of a LCD.