发明名称 プロセッサベースシステムハイブリッドリングバス相互接続、ならびに関連デバイス、プロセッサベースシステム、および方法
摘要 Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.
申请公布号 JP5968549(B2) 申请公布日期 2016.08.10
申请号 JP20150537736 申请日期 2013.10.09
申请人 クアルコム,インコーポレイテッド 发明人 ジャヤ・プラカシュ・スブラマニアム・ガナサン;マーク・マイケル・シェーファー;プルドゥヴィ・エヌ・ヌーニィ;ペリー・ウィルマン・リマクラス・ジュニア
分类号 G06F13/36;G06F13/38;H04L12/42 主分类号 G06F13/36
代理机构 代理人
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