Interchannel skew adjustment circuit

摘要

An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

主权项

1. An interchannel skew adjustment circuit comprising:
a phase adjustment circuit configured to receive a signal of a first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of a second channel, and detect a phase difference between these two signals; a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit; a PVT variation detection circuit configured to detect PVT variations of the phase adjustment circuit, and output PVT information indicating the PVT variations; and a PVT variation compensation circuit configured to compensate a control value output from the controller to the phase adjustment circuit based on the PVT information to control the delay amount in the phase adjustment circuit, wherein the PVT variation detection circuit includes
a delay circuit configured to receive a first signal, delay the first signal by a variable delay amount, and output a first delay signal,a flip-flop configured to receive the first delay signal as a data signal, and a second signal whose phase is shifted from a phase of the first signal by a predetermined amount as a clock signal, anda determiner configured to determine the PVT information based on an output of the flip-flop, andthe delay amount of the delay circuit is controlled with the PVT information determined by the determiner.