Patterning approach for improved via landing profile

摘要

The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

主权项

1. A semiconductor structure, comprising:
a semiconductor substrate; a first interconnect layer over the semiconductor substrate, the first interconnect layer comprising a first dielectric material having a metal body embedded therein, the metal body comprising a first sidewall and a second sidewall defining a first edge and a second edge, respectively, and a bottom surface, and a spacer element adjacent the metal body, the spacer element having a sidewall contiguous with the first sidewall of the metal body; a second interconnect layer overlying the first interconnect layer comprising a second dielectric material having at least one via therein, the at least one via filled with a conductive material which is electrically coupled to the metal body of the first interconnect layer; wherein the at least one via has a lower conductive portion which extends below an upper surface of the metal body; and a first barrier layer disposed along the second sidewall of the metal body and along a lower surface of the metal body and terminating at the spacer element without extending along the first sidewall of the metal body.