发明名称 METHOD FOR ORGANIZING, CONTROLLING, AND REPORTING ON DESIGN MISMATCH INFORMATION IN IC PHYSICAL DESIGN DATA
摘要 Systems and methods allow an IC design process to continue in the face of errors while those errors are being investigated and fixed in the actual design data. Potential mismatches can be categorized and a user can choose which action (if any) to take when a specific mismatch is discovered. A set of potential mismatches and their action settings can be aggregated into a higher level setting that the end user of the system can choose during different stages of a design project. A record of the mismatches that have been encountered, the design elements that are involved in each mismatch, and what action where taken to repair the mismatch is kept and maintained.
申请公布号 US2016092627(A1) 申请公布日期 2016.03.31
申请号 US201514868342 申请日期 2015.09.28
申请人 Synopsys, Inc. 发明人 Bales Mark William
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method for detecting and reporting design mismatch information in integrated circuit (IC) physical design data, comprising: receiving, at a computer, a set of design mismatch settings; creating, at the computer, one or more handlers based on the set of design mismatch settings; applying, by the computer, the one or more handlers to the physical design data; performing, by the computer, one or more actions with respect to one or more detected design mismatches; generating, by the computer, a record associated with the performed one or more actions.
地址 Mountain View CA US