Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer

摘要

An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.

主权项

1. An apparatus comprising:
a clock terminal configured to receive an external clock signal; a clock generator coupled to the clock terminal and configured to generate an internal clock signal in response to the external clock signal; a main clock line coupled to the clock generator at a first portion, the main clock line further includes a second portion and a third portion that is between the first and second portion; first and second output circuits arranged along the main clock line; a first clock line coupled to the third portion of the main clock line at one end thereof and coupled to the first output circuit at the other end thereof; and a second clock line coupled to the second portion of the main clock line at one end thereof and coupled to the second output circuit at the other end thereof, the first clock line is greater in length than the second clock line and the capacitance-resistance (CR) time constants of the first and second clock lines are substantially equal.