CHIP WITH PROGRAMMABLE SHELF LIFE

摘要

A structure includes a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD), a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect, a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect, a silicon dioxide layer above the first, second, third and fourth top metal layers, the silicon layer is in direct contact with the first and fourth top metal layers, and a barrier layer separating the silicon dioxide layer from each of the second and third top metal layers, a high resistance connection exist between the third top metal layer and the fourth top metal layer due to the presence of the silicon dioxide layer.

主权项

1. A structure comprising:
a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD); a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect; a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect; a silicon dioxide layer above the first, second, third and fourth top metal layers, the silicon dioxide layer is in direct contact with the first and fourth top metal layers; and a barrier layer separating the silicon dioxide layer from each of the second and third top metal layers, wherein a high resistance connection exist between the third top metal layer and the fourth top metal layer due to the presence of the silicon dioxide layer.