发明名称 並列多次元ワードアドレス可能メモリアーキテクチャ
摘要 PROBLEM TO BE SOLVED: To provide memory architecture optimized for random matrix operations.SOLUTION: An N-dimension addressable memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-dimension addressing (NDA), where N is at least two, and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
申请公布号 JP5859605(B2) 申请公布日期 2016.02.10
申请号 JP20140124468 申请日期 2014.06.17
申请人 クゥアルコム・インコーポレイテッドQUALCOMM INCORPORATED 发明人 チー−トゥン・チェン;インユプ・カン;ビラフォル・チャイヤクル
分类号 G11C11/413;G06F12/02 主分类号 G11C11/413
代理机构 代理人
主权项
地址