发明名称 |
METHOD TO IMPROVE MEMORY CELL ERASURE |
摘要 |
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided. |
申请公布号 |
US2016013195(A1) |
申请公布日期 |
2016.01.14 |
申请号 |
US201414326562 |
申请日期 |
2014.07.09 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Tsao Tsun-Kai;Tsair Yong-Shiuan;Shih Hung-Ling;Liu Po-Wei;Huang Wen-Tuo |
分类号 |
H01L27/115;H01L29/788;H01L21/3213;H01L21/28;H01L21/768;H01L23/528;H01L29/423;H01L29/66 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:
a semiconductor substrate including a first source/drain region and a second source/drain region; an erase gate located over the first source/drain region; and a floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. |
地址 |
Hsin-Chu TW |