| 摘要 |
The present invention provides a multi-channel time-interleaved analog-to-digital converter including: a clock generating circuit generating a work clock for the analog-to-digital converter; a channel ADC group including a number M of ADC channels configured to be a time-interleaved architecture, operating in turn in the way of time division multiplexing under the control of the clock generating circuit and converting one high speed analog input signal to a number M of low speed digital output signals, wherein the M is an integer not smaller than 2; a channel skew detecting circuit detecting the timing skew errors of the a number M of ADC channel output signals in real time, and acquiring the timing skew parameters of each ADC channel relative to a reference ADC channel; a signal compensation and reconstruction circuit compensating and reconstructing the digital output signals from the channel ADC group on the basis of the timing skew errors detected by the channel skew detecting circuit; a signal combination circuit combining the compensated a number M of low speed output signals of each channel generated by the signal compensation and reconstruction circuit and obtaining one high speed digital output signal finally. |
