| 摘要 |
An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41', 41'; 71, 71', 71'), each stage (41, 41', 41'; 71, 71', 71') comprising first (T1, T1', T1', etc.) and second transistors (T2, T2', T2'' etc.) having a common collector (52, 52', 52') and first (26, 26', 26') and second (36, 36', 36') emitters providing terminals (32, 42; 32', 42'; 32', 42') of each clamp stage (41, 41', 41'; 71, 71', 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42') of the last stage (41', 71') couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29', 29'; 39, 39', 39') (e.g., of poly SC) are coupled between the base (28, 28', 28'; 38, 38', 38') and emitter (26, 26', 26'; 36, 36', 36') of each transistor (T1, T1', T1'; T2, T2', T2'). Different resistor values (e.g., ~0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages (41, 41', 41'; 71, 71') gives even higher trigger voltages. The ESD trigger resistances (29, 29', 29'; 39, 39', 39') are desirably located outside the common collector-isolation wall (741, 742, 743; 741', 742', 743') surrounding the transistors (T1, T1', T1'; T2, T2', T2'). |
