Serial load leveling system and method

摘要

A load leveling system and method capable of controlling switches such that it appears to a generator that the load is constant. The purpose is to prevent high-load simultaneous switching or multiple synchronous switching from damaging sensitive equipment. The present invention utilizes a central controller communicating to a number of switches such that the switches turn off and on in a synchronized, serialized manner. As one switch turns “off,” another should be turning “on” until a cycle is completed. In this manner, the generator will only see a single “on” and a single “off” load per cycle. The various switches are scheduled such that, ideally, the power load seen by the power source has emissions of no more than one PWM load superpositioned with zero or more constant, non-modulated loads.

主权项

1. A serial load control subsystem for leveling a cumulative electrical load in a system including multiple, individual, electrical loads and a power source selectively connected to the electrical loads by the control subsystem, which load control subsystem includes:
a plurality of pulse-width modulation (PWM) switches each selectively connecting the power source and a respective individual electrical load; a controller adapted for programming with a PWM switch cycle schedule; said controller being connected to the PWM switch and adapted to provide scheduled switch signals to said PWM switch; said scheduled switch signals being adapted to control said PWM switch operation to minimize electromagnetic emissions from said system; said controller including a scheduling function adapted for calculating a schedule of opening and closing the plurality of switches to provide a minimum load variance among said plurality of switches; said scheduling function being adapted to open a respective switch when another switch closes; said processor including a wrap scheduling function adapted for accommodating a duty cycle for a switch if the duty cycle is less than a remaining PWM cycle: by providing a single On-time for a period; and by allocating any excess to the beginning of the PWM cycle; a central coordinator connected to said processor; said wrap scheduling function being accomplished by said central coordinator; said wrap scheduling function is accomplished by distributing control of each switch's PWM cycle to a respective individual switch; multiple control registers each connected to a respective PWM switch and adapted for maintaining an ON-time setting for a present PWM period which is less than a remaining PWM cycle; said control registers being adapted for loading with a next PWM period when an end value of a system PWM cycle is reached and the next PWM cycle is started; an additional register for implementing wrap scheduling by defining additional transitions occurring when an On-time is split; an array of registers adapted for scheduling initial On/Off states followed by phase settings causing the On/Off states to toggle as a PWM counter passes those settings; an array of registers adapted for scheduling pairs of subsequent turn-on and turn-off events as the PWM counter passes those settings; said processor includes a state logic function adapted for controlling said registers; said registers being buffered; a plurality of buffers adapted for being written to asynchronously with the PWM operations; said registers being updated with settings for the next PWM period without disrupting an ongoing PWM cycle; a token passing scheduling technique wherein each said PWM switch is provided with its own On-time duration and a first switch is synchronized to a common PWM cycle; as each switch finishes its On-time, it passes a token signal to a next switch permitting that switch to perform its On-time; an analog PWM system for aligning ramp oscillators whereby closing a switch results in opening another switch and starting a ramp cycle of the next switch; said processor including a rotational distribution for PWM load modulation remaining after serial load leveling whereby rotationally symmetric pulses transmit equal power; a PWM procedure is used for affecting smaller duty cycles; wherein said processor includes a delta-sigma modulation, pulse-density or pulse-coded modulation function for forming arbitrary waveforms; and a power cycling function sets an On-time of a designated first switch, which is adapted for generating tokens to control subsequent switch timings as duplicates of the first switch timing.